The present invention relates to a semiconductor device and to a technique which is effective when applied to, e.g., a semiconductor device including a circuit which transmits a signal at a high speed.
Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2003-264256 describes a semiconductor chip in which, in a first region adjacent to the middle region of a main surface, bump electrodes for inputting/outputting a data signal are disposed and, outside the first region, bump electrodes for inputting/outputting an address signal are disposed.
Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2008-311682) describes a structure in which, around a through conductor coupled to wires which transmit a differential signal, a plurality of through conductors supplied with a ground potential are arranged.
Patent Document 3 (Japanese Unexamined Patent Application Publication No. 2013-110293) describes a wiring substrate in which the width and thickness of a high-speed signal wire are larger than the width and thickness of a low-speed signal wire.